Responsible for high-performance and low power RFIC Transceiver Design for LTE, GNSS, Wi-Fi, Bluetooth, Zigbee and other communication systems. Be the Technical Lead for a team of talented and experienced RFIC/Analog design engineers while working closely with several cross functional teams (layout, digital and system).

Minimum Qualifications

• MS or PhD in Electrical Engineering with 12+ years of experience in RF/Analog IC design with advanced CMOS technology nodes. SOI technology experience a plus.
• Experience as Design Lead, Chip/Project Lead, Manager for RFIC products.
• Deep understanding of RFIC circuit design, and basic building blocks, including LNA, PA, Mixer, PLL, LC-VCO, LO Generation, VGA, Baseband Filters, TIA, LDO, Band-Gap and other baseband analog blocks.
• Good understanding of analog design concepts such as analysis of noise, linearity, mismatch, stability, offset and other analog impairments.
• Good understanding of CMOS device physics, RF device modeling, device noise parameters, inductor modeling and EM simulation.
• Knowledge of QFN & CSP packaging effects, supply isolations, circuit layout for optimum RF performance, EM effects, PEX (post-layout parasitic extraction).
• Familiar with various RF transceiver architectures and their trade-offs, as well as calibration methods used for various architectures.
• Experience in using development tools including Cadence Virtuoso, Spectre RF, EMX & MATLAB.
• Understanding of system specifications and ability to translate system requirement into circuit requirement at IC level. Deep knowledge of RF concepts including S-parameters, NF, Stability, P1dB, HD, IMD, IIP2/3.
• Hands-on experience in silicon characterization and debug.
• Team player with good verbal and written communication skills along with excellent presentations skills (MS Office Suite). Strong sense of urgency.

Desired Qualifications

• 15+ years of RF/Analog IC design.
• RFIC and Power Management experience.

Remote (hybrid) option for the right candidate(s).