Sr Test engineer / Principal Test engineer on Advantest 93K

for the Fremont area. 

The person performing this job will interface with Design on Testability including Scan and Bist. Prepare schematics for ATE test boards, Do the pin mapping for optimum tester resources including Analog test resources. The person will do coding, Verification offline/On tester on complex SOC. Debug and Characterization. 

Responsibilities:

• Create documentation for product test plans and test methodologies to meet product specification.
• Involve in testability review, such as DFT and DFM and analog test methods and testing
• Design tester hardware for high speed, Analog and RF (desirable) products
• Test patterns translation from design simulation environment to ATE format.
• Develop characterization, production, and wafer sort test programs.
• Test time reduction, yield improvement, and release of production test programs with product engineers.

Requirements/Education:

• Minimum 5+ years of test program development experience on the Advantest 93K ATE test platform.
• Strong knowledge of C/C++, Perl, Unix and Linux environment.
• BS or MS